1. Field of the Invention
The present invention relates to a microcomputer coupled to an external bus accessible from an external apparatus, and more particularly, to such a microcomputer adapted to be put in a wait condition when the right of using the external bus of the microcomputer is temporarily assigned to the external apparatus that has requested access to another external apparatus coupled to the external bus, without intermediary of the microcomputer.
2. Description of related art
At present, various types of microcomputers have been widely used. Most of microcomputers are of the stored program control type, and therefore, the processing speed is essentially defined by the speed at which the programs are executed by a central processing unit (CPU) contained in the microcomputers. On the other hand, these microcomputers are frequently used in combination with external apparatuses such as input/output devices, peripheral controllers, external memories, and others. Among these external apparatuses which are coupled with the microcomputers by an external bus, there are not only high speed devices but also low speed devices. Data transfer speed between two different apparatuses is determined by the slower device. Therefore, when a substantial amount of data is transferred between the microcomputer and an external apparatus which is typified by mass storages such as minidrums, floppy disks and magnetic disks, the data transfer speed is limited by the processing speed of the external apparatus. This is a waste of time to the microcomputer itself, because the microcomputer is inoperative during the data transfer.
In order to resolve this problem, a direct access of an external apparatus is performed without the intermediary of the microcomputer, so that the data transfer between the external apparatuses can be effected regardless of the microcomputer's operation.
This method is generally called a "direct memory access" (DMA). In this case, a microcomputer is coupled with an external memory via an external bus, and a direct memory access controller is coupled to the external bus together with an external apparatus, so as to request an external bus access to the microcomputer when the DMA data transfer is requested. Briefly, when a data transfer is requested from an input/output (I/O) interface, the DMA controller applies a HOLD command to the microcomputer. In response to the HOLD command, the microcomputer outputs a HOLD acknowledge (HOLDA) signal to the DMA controller and enters a HOLD state isolated from the external bus with regard to data transmission. Thus, the DMA controller obtains the right of controlling the external bus, and then, causes the external memory to couple with the external bus, so that the data transfer is effected between the external memory and the I/O interface without intermediary of the microcomputer. In other words, the microcomputer is placed in a HOLD state with regard to bus access, and the bus control right is assigned from the microcomputer to the DMA controller.
In this HOLD condition, the microcomputer continues to execute its operation (which does not need the access to the external bus), and when the operation needs access to the external bus the microcomputer actually enters the true or full HOLD state not only as to bus access but in respect to all operations.
After the DMA operation is completed, the DMA controller operates to separate the data transmission relation between the external memory and the I/O interface, and to reset the HOLD signal to the microcomputer. As a result, the microcomputer is released from the HOLD state and obtains the external bus control right. At the same time, the microcomputer resets the HOLDA signal, and starts the program operation. Specifically, since the microcomputer holds or stops operations when it needed access of the external bus, the microcomputer must first execute the address computation for an external apparatus to which the access is requested, after the external bus access right has been obtained. This will take an additional period of time corresponding to two or more clock cycles from the moment the HOLD command is reset. This additional time causes lowering of processing speed of the microcomputer, and is not negligible in modern microcomputers in which the DMA is frequently requested.